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收看在线演示的要求和说明：计算机安装微软 Media Player软件，并以宽带接入Internat.。其中Altera和Lattice培训内容可以从本页面直接点击，无需注册，Xilinx培训内容提供连接。 所有内容均为英文。 |
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基于QuartusII软件的FPGA/CPLD基本设计流程
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QuartusII软件设计流程
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QuartusII设计优化技巧
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如何利用QuartusII减少设计周期,达到时序要求
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QuartusII的设计仿真和校验
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NiosII嵌入式软处理器开发流程
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This comprehensive demo takes you through the 533 Mbps DDR2 SDRAM memory interface design using the Memory Interface Generator, a hardware system verification for the 300 MHz QDR II SRAM interface design using the ChipScope Pro in circuit analyzer and the Xilinx Advanced Memory Development System. Included is also an overview of the complete Memory Interface solutions using the Virtex-4 FPGA. |
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This in-depth session shows how the Virtex-4 family of platform FPGAs delivers twice the density, twice the performance, with half the power consumption of any other FPGA family. Available in three platforms with 200,000 logic cells, 500 MHz performance, you can select the device that most cost-effectively implements your application. Virtex-4 brings new levels of performance and value by combining the revolutionary ASMBL architecture with 90nm process, copper metallization, and 300mm wafer technologies. |
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This comprehensive demo takes you through the system verification of the DDR SDRAM design using the ChipScope Pro in circuit analyzer and the Xilinx evaluation board for 200 MHZ (400 Mbps) DDR SDRAM. Included is also an overview of the 200 MHz (400 Mbps) DDR SDRAM and 200 MHz (800 Mbps) QDR II SRAM hardware solutions using the Virtex-II Pro FPGA device. |
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This in-depth demo reviews the features of our UltraController embedded processor solution that provides a complete reference design, with documentation, to be utilized as a lightweight PowerPC? microcontroller. The 32-bit input / 32-bit output design created as a simple block, ready to integrate into larger designs, requires only a reset and a clock input. |
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EasyPath solution gives you the easiest, lowest-cost, lowest-risk, cost reduction path for FPGA volume production. The Virtex-II Series EasyPath solution leverages proven application-specific FPGA test methods to lower unit costs. The unique Xilinx-developed process tests for only the FPGA resources used by a specific design. |
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See this video overview of the MicroBlaze soft processor solution, the industry's fastest 32-bit soft processor core delivering up to 123 Dhrystone MIPS at 150 MHz on a Virtex-II Pro FPGA device. |
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This demo takes you through the steps of using the Xilinx Embedded Development Kit tools and the Platform Studio IDE to build a simple webserver application based on the MicroBlaze soft processor and its peripherals in the Virtex-II Pro FPGA. |
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This real-time product demonstration shows the PlanAhead methodology and how it can help you dramatically decrease design time and achieve superior results. By providing a faster, less iterative path from logic synthesis through physical design, PlanAhead lets you quickly and consistently achieve your design requirements, even in the face of repeated design changes. You can quickly examine "what if" scenarios, enabling you to identify and fix potential problems early. With it's seamless integration within the ISE design flow, PlanAhead offers support for the leading Xilinx FPGA devices, including Spartan-3, Virtex-II, Virtex-II Pro, and the new, multi-platform Virtex-4 FPGA families. |
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This real-time product demonstration lets you see how ISE 6, the Integrated Software Environment from Xilinx, offers the fastest, most complete, integrated family of design tools available anywhere. When used with the new Virtex-4? FPGA family, ISE 6 lets designers achieve the fastest performance in the market today with up to 200,000 logic cells and up to 500 MHz performance. Together, Virtex-4 and ISE 6 deliver twice the density and faster performance of any other FPGA offering. |
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View this demo to see how ChipScope Pro tools can be used to shorten the debug and verification phase of a Xilinx FPGA design. This demonstration will use ChipScope ILA and VIO cores to gain on-chip visibly into a Xilinx Virtex-4 design. See advanced capabilities and features that allow the user to optimize on-chip resources. More integrated IP, high performance, and advanced interfaces result in a more challenging debug and verification process. See how Xilinx's ChipScope Pro tools slash debug and verification times, shortening the overall FPGA design time. |
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ChipScope PRO—Accelerating On-chip Debug & Verification
Brent Przybus, Advanced Products Division, Product Marketing Mgr.
This in-depth demo shows how ChipScope Pro, the real-time debug and verification tool for Xilinx FPGAs, enables on-chip debug at or near operating system speed. The size, speed, and board requirements of today's FPGAs make it nearly impossible to debug designs using traditional logic analysis methods. Flip-chip and ball grid array packaging do not have exposed leads that can be physically probed. Xilinx has the solution: ChipScope Pro. |
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| In this engaging demonstration, DSP applications engineer Niall Battson, explains how to "Harness the power of the Virtex-4 Xtreme DSP Slice" to enable you to achieve 500MHz filter performance, significantly lower power consumption and efficiently implement your DSP designs. |
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| This Demo shows you how an FPGA device can be used for signal processing and provides an overview of the Xilinx DSP solution including the IP cores that are available as algorithms and DSP software. |
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This module explains spectrum channelization for wired and wireless applications using a number of examples built using the Xilinx System Generator for DSP and the Xilinx DSP IP library. |
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This compelling Demo shows the implementation of a QAM receiver including both synchronization and adaptive channel equalization. |
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Here are some tips on how to implement signal processing functions onto FPGAs. Moving signals to baseband, filtering tricks, decimating and DFT implementation are all covered in this dynamic whiteboard session. |
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This demo shows how System Generator for DSP—our high-level modeling environment for DSP data paths—yields performance and efficiency comparable to hand-crafted designs. Because of its tight integration with the Simulink? and MATLAB? tools from The Mathworks, FPGA designs are implemented in a familiar setting without concern for the underlying hardware details. |
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