//
//
//-----------------------------------------------------------------------------------
// DESCRIPTION   :  Flip-flop D type
//                  Width : 8
//                  CLK active : high
//                  CLR active : high
//                  CLR type : synchronous
//                  SET active : high
//                  SET type : synchronous
//                  LOAD active : high
//                  CE active : high
//
// Download from :  http://www.pld.com.cn
//-----------------------------------------------------------------------------------


module ffd (CLR , SET , CE , LOAD , DATA_IN , DATA_OUT , CLK );
input CLR , SET , CE , LOAD , CLK ;
input [7:0] DATA_IN ;
output [7:0] DATA_OUT ;


reg [7:0] DATA_OUT_TEMP;

	always @(posedge CLK )
	begin
		if (CE == 1'b1)
			if (CLR == 1'b1)
				DATA_OUT_TEMP = {8{1'b0}};
			else if (SET == 1'b1)
				DATA_OUT_TEMP = {8{1'b1}};
			else if (LOAD == 1'b1)
				DATA_OUT_TEMP = DATA_IN ;
	end

	assign DATA_OUT = DATA_OUT_TEMP;

endmodule
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