--
--
---------------------------------------------------------------------------------------
-- DESCRIPTION   :  Shift register
--                  Type : univ
--                  Width : 4
--                  Shift direction: right/left (right active high)
--
--                  CLK active : high
--                  CLR active : high
--                  CLR type : synchronous
--                  SET active : high
--                  SET type : synchronous
--                  LOAD active : high
--                  CE active : high
--                  SERIAL input : SI
--
-- Download from :  http://www.pld.com.cn
---------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;

entity shft_reg is
	port (
		DIR : in std_logic;
		CLK : in std_logic;
		CLR : in std_logic;
		SET : in std_logic;
		CE : in std_logic;
		LOAD : in std_logic;
		SI : in std_logic;
		DATA : in std_logic_vector(3 downto 0);
		data_out : out std_logic_vector(3 downto 0)
	);
end entity;



architecture shft_reg_arch of shft_reg is
signal TEMP_data_out : std_logic_vector(3 downto 0);
begin

	process(CLK)
	begin
		if rising_edge(CLK) then
			if CE = '1' then
				if CLR = '1' then
					TEMP_data_out <= "0000";
				elsif SET = '1' then
					TEMP_data_out <= "1111";
				elsif LOAD = '1' then
					TEMP_data_out <= DATA;
				else
					if DIR = '1' then
						TEMP_data_out <= SI & TEMP_data_out(3 downto 1);
					else
						TEMP_data_out <= TEMP_data_out(2 downto 0) & SI;
					end if;
				end if;
			end if;
		end if;
	end process;

	data_out <= TEMP_data_out;

end architecture;
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